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lavu/float_dsp: fix compilation with RISC-V ILP32 ABI

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Rémi Denis-Courmont 2024-11-20 20:30:56 +02:00
parent da1ab7940e
commit 63922ba5dc
1 changed files with 16 additions and 0 deletions
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16
libavutil/riscv/float_dsp_rvv.S
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@ -227,7 +227,15 @@ endfunc
// (a0) += (a1) * fa0 [0..a2-1] // (a0) += (a1) * fa0 [0..a2-1]
func ff_vector_dmac_scalar_rvv, zve64d, zba func ff_vector_dmac_scalar_rvv, zve64d, zba
lpad 0 lpad 0
#if __riscv_xlen >= 64
NOHWD fmv.d.x fa0, a2 NOHWD fmv.d.x fa0, a2
#else
NOHWD addi sp, sp, -16
NOHWD sw a0, 0(sp)
NOHWD sw a1, 4(sp)
NOHWD fld fa0, (sp)
NOHWD addi sp, sp, 16
#endif
NOHWD mv a2, a3 NOHWD mv a2, a3
1: 1:
vsetvli t0, a2, e64, m8, ta, ma vsetvli t0, a2, e64, m8, ta, ma
@ -246,7 +254,15 @@ endfunc
// (a0) = (a1) * fa0 [0..a2-1] // (a0) = (a1) * fa0 [0..a2-1]
func ff_vector_dmul_scalar_rvv, zve64d, zba func ff_vector_dmul_scalar_rvv, zve64d, zba
lpad 0 lpad 0
#if __riscv_xlen >= 64
NOHWD fmv.d.x fa0, a2 NOHWD fmv.d.x fa0, a2
#else
NOHWD addi sp, sp, -16
NOHWD sw a0, 0(sp)
NOHWD sw a1, 4(sp)
NOHWD fld fa0, (sp)
NOHWD addi sp, sp, 16
#endif
NOHWD mv a2, a3 NOHWD mv a2, a3
1: 1:
vsetvli t0, a2, e64, m8, ta, ma vsetvli t0, a2, e64, m8, ta, ma