forked from FFmpeg/FFmpeg
aarch64/vvc: Add put_qpel_vx
put_luma_v_8_4x4_c: 1.0 ( 1.00x) put_luma_v_8_4x4_neon: 0.0 ( 0.00x) put_luma_v_8_8x8_c: 3.5 ( 1.00x) put_luma_v_8_8x8_neon: 0.5 ( 7.00x) put_luma_v_8_16x16_c: 13.8 ( 1.00x) put_luma_v_8_16x16_neon: 1.2 (11.00x) put_luma_v_8_32x32_c: 54.2 ( 1.00x) put_luma_v_8_32x32_neon: 5.0 (10.85x) put_luma_v_8_64x64_c: 217.5 ( 1.00x) put_luma_v_8_64x64_neon: 18.8 (11.60x) put_luma_v_8_128x128_c: 886.2 ( 1.00x) put_luma_v_8_128x128_neon: 74.0 (11.98x)
This commit is contained in:
Zhao Zhili
Nuo Mi
parent
b051bc7cb8
commit
a0b52afd32
3 changed files with 115 additions and 0 deletions
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@ -274,4 +274,12 @@ NEON8_FNPROTO_PARTIAL_6(qpel_h, (int16_t * dst,
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const uint8_t *_src, ptrdiff_t _srcstride, int height,
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const int8_t *hf, const int8_t *vf, int width), _i8mm);
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void ff_vvc_put_qpel_v4_8_neon(int16_t *dst, const uint8_t *_src,
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ptrdiff_t _srcstride, int height,
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const int8_t *hf, const int8_t *vf, int width);
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void ff_vvc_put_qpel_v8_8_neon(int16_t *dst, const uint8_t *_src,
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ptrdiff_t _srcstride, int height,
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const int8_t *hf, const int8_t *vf, int width);
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#endif
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@ -86,6 +86,11 @@ endconst
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sxtl v0.8h, v0.8b
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.endm
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.macro vvc_load_qpel_filterh freg
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ld1 {v0.8b}, [\freg]
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sxtl v0.8h, v0.8b
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.endm
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.macro calc_qpelh dst, src0, src1, src2, src3, src4, src5, src6, src7, op, shift=6
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smull \dst\().4s, \src0\().4h, v0.h[0]
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smlal \dst\().4s, \src1\().4h, v0.h[1]
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@ -95,11 +100,15 @@ endconst
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smlal \dst\().4s, \src5\().4h, v0.h[5]
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smlal \dst\().4s, \src6\().4h, v0.h[6]
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smlal \dst\().4s, \src7\().4h, v0.h[7]
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.ifc \op, sqxtn
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sqxtn \dst\().4h, \dst\().4s
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.else
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.ifc \op, sshr
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sshr \dst\().4s, \dst\().4s, \shift
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.else
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\op \dst\().4h, \dst\().4s, \shift
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.endif
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.endif
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.endm
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.macro calc_qpelh2 dst, dstt, src0, src1, src2, src3, src4, src5, src6, src7, op, shift=6
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@ -111,11 +120,15 @@ endconst
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smlal2 \dstt\().4s, \src5\().8h, v0.h[5]
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smlal2 \dstt\().4s, \src6\().8h, v0.h[6]
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smlal2 \dstt\().4s, \src7\().8h, v0.h[7]
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.ifc \op, sqxtn2
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sqxtn2 \dst\().8h, \dstt\().4s
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.else
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.ifc \op, sshr
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sshr \dst\().4s, \dstt\().4s, \shift
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.else
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\op \dst\().8h, \dstt\().4s, \shift
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.endif
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.endif
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.endm
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.macro calc_all
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@ -1000,6 +1013,93 @@ function ff_hevc_put_hevc_qpel_v64_8_neon, export=1
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ret
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endfunc
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/* ff_hevc_put_hevc_qpel_vx require filter parameters be
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* [-, +, -, +, +, -, +, -],
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* vvc doesn't meet the requirement.
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*/
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function ff_vvc_put_qpel_v4_8_neon, export=1
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vvc_load_qpel_filterh x5
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sub x1, x1, x2, lsl #1
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mov x9, #(VVC_MAX_PB_SIZE * 2)
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sub x1, x1, x2
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ldr s16, [x1]
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ldr s17, [x1, x2]
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add x1, x1, x2, lsl #1
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ldr s18, [x1]
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ldr s19, [x1, x2]
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uxtl v16.8h, v16.8b
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uxtl v17.8h, v17.8b
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add x1, x1, x2, lsl #1
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ldr s20, [x1]
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ldr s21, [x1, x2]
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uxtl v18.8h, v18.8b
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uxtl v19.8h, v19.8b
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add x1, x1, x2, lsl #1
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ldr s22, [x1]
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add x1, x1, x2
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uxtl v20.8h, v20.8b
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uxtl v21.8h, v21.8b
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uxtl v22.8h, v22.8b
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.macro calc tmp, src0, src1, src2, src3, src4, src5, src6, src7
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ld1 {\tmp\().s}[0], [x1], x2
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uxtl \tmp\().8h, \tmp\().8b
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calc_qpelh v24, \src0, \src1, \src2, \src3, \src4, \src5, \src6, \src7, sqxtn
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subs w3, w3, #1
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st1 {v24.4h}, [x0], x9
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.endm
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1:
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calc_all
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.purgem calc
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2:
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ret
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endfunc
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function ff_vvc_put_qpel_v8_8_neon, export=1
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vvc_load_qpel_filterh x5
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sub x1, x1, x2, lsl #1
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sub x1, x1, x2
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mov x9, #(VVC_MAX_PB_SIZE * 2)
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0:
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mov x8, x1
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ldr d16, [x8]
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ldr d17, [x8, x2]
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mov x10, x0
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mov w11, w3
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add x8, x8, x2, lsl #1
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ldr d18, [x8]
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ldr d19, [x8, x2]
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uxtl v16.8h, v16.8b
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uxtl v17.8h, v17.8b
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add x8, x8, x2, lsl #1
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ldr d20, [x8]
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ldr d21, [x8, x2]
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uxtl v18.8h, v18.8b
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uxtl v19.8h, v19.8b
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add x8, x8, x2, lsl #1
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ldr d22, [x8]
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add x8, x8, x2
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uxtl v20.8h, v20.8b
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uxtl v21.8h, v21.8b
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uxtl v22.8h, v22.8b
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.macro calc tmp, src0, src1, src2, src3, src4, src5, src6, src7
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ld1 {\tmp\().8b}, [x8], x2
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uxtl \tmp\().8h, \tmp\().8b
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calc_qpelh v24, \src0, \src1, \src2, \src3, \src4, \src5, \src6, \src7, sqxtn
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calc_qpelh2 v24, v25, \src0, \src1, \src2, \src3, \src4, \src5, \src6, \src7, sqxtn2
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subs w11, w11, #1
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st1 {v24.8h}, [x10], x9
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.endm
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1:
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calc_all
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.purgem calc
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2:
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subs w6, w6, #8
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add x0, x0, #16
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add x1, x1, #8
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b.ne 0b
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ret
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endfunc
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function ff_hevc_put_hevc_qpel_bi_v4_8_neon, export=1
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load_qpel_filterb x7, x6
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sub x2, x2, x3, lsl #1
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@ -60,6 +60,13 @@ void ff_vvc_dsp_init_aarch64(VVCDSPContext *const c, const int bd)
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c->inter.put[0][5][0][1] =
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c->inter.put[0][6][0][1] = ff_vvc_put_qpel_h32_8_neon;
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c->inter.put[0][1][1][0] = ff_vvc_put_qpel_v4_8_neon;
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c->inter.put[0][2][1][0] =
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c->inter.put[0][3][1][0] =
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c->inter.put[0][4][1][0] =
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c->inter.put[0][5][1][0] =
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c->inter.put[0][6][1][0] = ff_vvc_put_qpel_v8_8_neon;
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c->inter.put_uni[0][1][0][0] = ff_vvc_put_pel_uni_pixels4_8_neon;
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c->inter.put_uni[0][2][0][0] = ff_vvc_put_pel_uni_pixels8_8_neon;
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c->inter.put_uni[0][3][0][0] = ff_vvc_put_pel_uni_pixels16_8_neon;
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