forked from FFmpeg/FFmpeg
305 lines
9.4 KiB
ArmAsm
305 lines
9.4 KiB
ArmAsm
/*
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* Copyright (c) 2024 Institue of Software Chinese Academy of Sciences (ISCAS).
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "libavcodec/riscv/h26x/asm.S"
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.macro avg w, vlen, id
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\id\w\vlen:
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.if \w < 128
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vsetvlstatic16 \w, \vlen
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addi t0, a2, 128*2
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addi t1, a3, 128*2
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add t2, a0, a1
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vle16.v v0, (a2)
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vle16.v v8, (a3)
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addi a5, a5, -2
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vle16.v v16, (t0)
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vle16.v v24, (t1)
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vadd.vv v8, v8, v0
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vadd.vv v24, v24, v16
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vmax.vx v8, v8, zero
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vmax.vx v24, v24, zero
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vsetvlstatic8 \w, \vlen
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addi a2, a2, 128*4
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vnclipu.wi v8, v8, 7
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vnclipu.wi v24, v24, 7
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addi a3, a3, 128*4
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vse8.v v8, (a0)
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vse8.v v24, (t2)
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sh1add a0, a1, a0
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.else
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addi a5, a5, -1
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mv t1, a0
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mv t2, a2
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mv t3, a3
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mv t4, a4
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1:
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vsetvli t0, a4, e16, m8, ta, ma
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sub a4, a4, t0
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vle16.v v0, (a2)
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vle16.v v8, (a3)
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vadd.vv v8, v8, v0
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vmax.vx v8, v8, zero
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vsetvli zero, zero, e8, m4, ta, ma
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vnclipu.wi v8, v8, 7
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vse8.v v8, (a0)
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sh1add a2, t0, a2
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sh1add a3, t0, a3
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add a0, a0, t0
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bnez a4, 1b
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add a0, t1, a1
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addi a2, t2, 128*2
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addi a3, t3, 128*2
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mv a4, t4
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.endif
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bnez a5, \id\w\vlen\()b
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ret
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.endm
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.macro func_avg vlen
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func ff_vvc_avg_8_rvv_\vlen\(), zve32x, zbb, zba
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lpad 0
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POW2_JMP_TABLE 1, \vlen
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csrwi vxrm, 0
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POW2_J \vlen, 1, a4
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.irp w,2,4,8,16,32,64,128
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avg \w, \vlen, 1
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.endr
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endfunc
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.endm
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func_avg 128
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func_avg 256
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#if (__riscv_xlen == 64)
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.macro w_avg w, vlen, id
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\id\w\vlen:
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.if \w <= 32 || (\w == 64 && \vlen == 256)
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vsetvlstatic16 \w, \vlen
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addi t0, a2, 128*2
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addi t1, a3, 128*2
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vle16.v v0, (a2)
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vle16.v v4, (a3)
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addi a5, a5, -2
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vle16.v v8, (t0)
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vle16.v v12, (t1)
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vwmul.vx v16, v0, a7
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vwmul.vx v24, v8, a7
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vwmacc.vx v16, t3, v4
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vwmacc.vx v24, t3, v12
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vsetvlstatic32 \w, \vlen
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add t2, a0, a1
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vadd.vx v16, v16, t4
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vadd.vx v24, v24, t4
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vsetvlstatic16 \w, \vlen
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vnsrl.wx v16, v16, t6
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vnsrl.wx v24, v24, t6
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vmax.vx v16, v16, zero
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vmax.vx v24, v24, zero
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vsetvlstatic8 \w, \vlen
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addi a2, a2, 128*4
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vnclipu.wi v16, v16, 0
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vnclipu.wi v24, v24, 0
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vse8.v v16, (a0)
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addi a3, a3, 128*4
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vse8.v v24, (t2)
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sh1add a0, a1, a0
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.else
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addi a5, a5, -1
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mv t1, a0
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mv t2, a2
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mv t5, a3
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mv a6, a4
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1:
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vsetvli t0, a4, e16, m4, ta, ma
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sub a4, a4, t0
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vle16.v v0, (a2)
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vle16.v v4, (a3)
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vwmul.vx v16, v0, a7
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vwmacc.vx v16, t3, v4
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vsetvli zero, zero, e32, m8, ta, ma
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vadd.vx v16, v16, t4
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vsetvli zero, zero, e16, m4, ta, ma
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vnsrl.wx v16, v16, t6
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vmax.vx v16, v16, zero
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vsetvli zero, zero, e8, m2, ta, ma
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vnclipu.wi v16, v16, 0
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vse8.v v16, (a0)
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sh1add a2, t0, a2
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sh1add a3, t0, a3
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add a0, a0, t0
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bnez a4, 1b
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add a0, t1, a1
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addi a2, t2, 128*2
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addi a3, t5, 128*2
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mv a4, a6
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.endif
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bnez a5, \id\w\vlen\()b
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ret
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.endm
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.macro func_w_avg vlen
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func ff_vvc_w_avg_8_rvv_\vlen\(), zve32x, zbb, zba
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lpad 0
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POW2_JMP_TABLE 2, \vlen
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csrwi vxrm, 0
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addi t6, a6, 7
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ld t3, (sp)
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ld t4, 8(sp)
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ld t5, 16(sp)
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addi t4, t4, 1 // o0 + o1 + 1
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add t4, t4, t5
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addi t5, t6, -1 // shift - 1
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sll t4, t4, t5
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POW2_J \vlen, 2, a4
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.irp w,2,4,8,16,32,64,128
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w_avg \w, \vlen, 2
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.endr
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endfunc
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.endm
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func_w_avg 128
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func_w_avg 256
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#endif
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func dmvr zve32x, zbb, zba
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lpad 0
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li t0, 4
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1:
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add t1, a1, a2
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addi t4, a0, 128*2
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vle8.v v0, (a1)
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vle8.v v4, (t1)
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addi a3, a3, -2
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vwmulu.vx v16, v0, t0
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vwmulu.vx v20, v4, t0
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vse16.v v16, (a0)
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vse16.v v20, (t4)
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sh1add a1, a2, a1
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add a0, a0, 128*2*2
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bnez a3, 1b
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ret
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endfunc
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.macro dmvr_h_v mn, type, w, vlen
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func dmvr_\type\vlen\w, zve32x, zbb, zba
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lla t4, ff_vvc_inter_luma_dmvr_filters
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sh1add t4, \mn, t4
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lbu t5, (t4)
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lbu t6, 1(t4)
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1:
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vsetvlstatic8 \w, \vlen
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.ifc \type,h
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addi t0, a1, 1
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addi t1, a1, 2
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.else
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add t0, a1, a2
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add t1, t0, a2
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.endif
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vle8.v v0, (a1)
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vle8.v v4, (t0)
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vle8.v v8, (t1)
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addi a3, a3, -2
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addi t2, a0, 128*2
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vwmulu.vx v12, v0, t5
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vwmulu.vx v24, v4, t5
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vwmaccu.vx v12, t6, v4
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vwmaccu.vx v24, t6, v8
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vsetvlstatic16 \w, \vlen
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vssrl.vi v12, v12, 2
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vssrl.vi v24, v24, 2
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vse16.v v12, (a0)
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vse16.v v24, (t2)
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add a0, a0, 128*4
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sh1add a1, a2, a1
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bnez a3, 1b
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ret
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endfunc
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.endm
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.macro dmvr_load_h dst, filter0, filter1, w, vlen
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vsetvlstatic8 \w, \vlen
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addi a6, a1, 1
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vle8.v \dst, (a1)
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vle8.v v2, (a6)
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vwmulu.vx v4, \dst, \filter0
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vwmaccu.vx v4, \filter1, v2
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vsetvlstatic16 \w, \vlen
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vssrl.vi \dst, v4, 2
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.endm
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.macro dmvr_hv w, vlen
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func dmvr_hv\vlen\w, zve32x, zbb, zba
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lla t0, ff_vvc_inter_luma_dmvr_filters
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sh1add t1, a4, t0
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sh1add t2, a5, t0
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lbu t3, (t1) // filter[mx][0]
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lbu t4, 1(t1) // filter[mx][1]
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lbu t5, (t2) // filter[my][0]
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lbu t6, 1(t2) // filter[my][1]
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dmvr_load_h v12, t3, t4, \w, \vlen
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add a1, a1, a2
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1:
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vmul.vx v28, v12, t5
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addi a3, a3, -1
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dmvr_load_h v12, t3, t4, \w, \vlen
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vmacc.vx v28, t6, v12
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vssrl.vi v28, v28, 4
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vse16.v v28, (a0)
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add a1, a1, a2
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addi a0, a0, 128*2
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bnez a3, 1b
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ret
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endfunc
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.endm
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.macro func_dmvr vlen, name
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func ff_vvc_\name\()_8_rvv_\vlen\(), zve32x, zbb, zba
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lpad 0
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li t0, 20
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beq a6, t0, DMVR\name\vlen\()20
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.irp w,12,20
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DMVR\name\vlen\w:
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.ifc \name, dmvr
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vsetvlstatic8 \w, \vlen
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j \name
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.else
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csrwi vxrm, 0
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j \name\()\vlen\w
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.endif
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.endr
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endfunc
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.endm
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.irp vlen,256,128
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.irp w,12,20
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dmvr_h_v a4, h, \w, \vlen
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dmvr_h_v a5, v, \w, \vlen
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dmvr_hv \w, \vlen
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.endr
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func_dmvr \vlen, dmvr
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func_dmvr \vlen, dmvr_h
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func_dmvr \vlen, dmvr_v
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func_dmvr \vlen, dmvr_hv
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.endr
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func_put_pixels 256, 128, vvc
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func_put_pixels 128, 128, vvc
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